VLSI Test Principles and Architectures: Design for Testability by Wen Xiaoqing

Author:Wen, Xiaoqing...
Language: eng
Format: epub
Published: 2014-05-22T17:42:17.646000+00:00

For systems that include concurrent checking circuits, it is possible to use the circuitry to verify the output response during explicit (offline) testing; hence, the need to implement a separate response analysis circuit, such as a MISR, is avoided.

Concurrent Self-Verification

A BIST architecture shown in Figure 5.45, concurrent self-verification (CSV), was described in [Sedmak 1979] and [Sedmak 1980]. A PRPG is applied to the functional circuitry (CUT) and the duplicate circuitry. The duplicate circuitry is realized in complementary form to reduce design and common-mode faults. Because the checking circuitry recommended involves comparing the outputs of the two implementations, this technique avoids the aliasing problem and consequent loss of effective fault coverage. The checking circuitry is a totally self-checking two-rail checker [Abramovici 1994].

Download

Copyright Disclaimer:
This site does not store any files on its server. We only index and link to content provided by other sites. Please contact the content providers to delete copyright contents if any and email us, we'll remove relevant links or contents immediately.